In the case of conventional memory devices, in particular conventional semiconductor memory devices, it is sometimes common to differentiate between functional memory devices (e.g., PLAs, PALs, etc.) and table memory devices. For example, some table memory devices include ROM devices (Read Only Memory) and RAM devices (Random Access Memory or read-write memory) such as DRAMs and SRAMs.
In the case of SRAMs (Static Random Access Memory), individual memory cells typically comprise, for example, six transistors configured as a cross-coupled latch. In the case of DRAMs (Dynamic Random Access Memory), generally only one single, correspondingly controlled capacitive element (e.g., the gate-source capacitance of a MOSFET) is employed, wherein charge may be stored in the capacitance. The charge in a DRAM, however, remains for only a short time, and a periodic refresh must be performed, to maintain a data state. In contrast to the DRAM, the SRAM requires no refresh, and the data stored in the memory cell remains stored as long as an appropriate supply voltage is fed to the SRAM. Both SRAMs and DRAMs are considered volatile memories, wherein a data state is only retained as long as power is supplied thereto.
In contrast to volatile memory, non-volatile memory devices (NVMs) exhibit a different property, wherein the stored data is retained even when the supply voltage associated therewith is switched off. This type of memory has several advantages for various types of mobile communications devices such as, for example, in an electronic rolodex on cell phones, wherein the data therein is retained even when the cell phone is turned off.
One type of non-volatile memory is called resistive or resistively switching memory devices. In such a resistive memory, a memory material positioned between two appropriate electrodes (i.e., an anode and a cathode) is placed, by appropriate switching processes, in a more or less conductive state, wherein the more conductive state corresponds, for example, to a logic “1”, and the less conductive state corresponds, for example, to a logic “0” (or vice versa). Suitable resistive memories can be, for example, perovskite memory, as described in W. W. Zhuang et al., “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM 2002, resistive switching in binary oxides (OxRAM), for example, as described in I. G. Baek et. al., “Multi-layer crosspoint binary oxide resistive memory (OxRAM) for post-NAND storage application”, IEDM 2005, phase change memory (PCRAM), and conductive bridging RAM (CBRAM), as described in M. Kund et al., “Conductive bridging RAM (CBRAM): An emerging non-volatile memory technology scalable to sub 20 nm”, IEDM, 2005.
In the case of phase change memory, an appropriate chalcogenide compound (e.g., a GeSbTe or an AgInSbTe compound) may, for instance, be used as the active material that is positioned between the two corresponding electrodes. The chalcogenide compound material can be placed in an amorphous, i.e., relatively weakly conductive, or a crystalline, i.e., relatively strongly conductive state by means of appropriate switching processes, and thus behaves like a variable resistance element, which as highlighted above, may be exploited as differing data states.
In order to achieve a change in the phase change material from an amorphous state to a crystalline state, an appropriate heating current is applied to the electrodes, wherein the current heats the phase change material beyond the crystallization temperature thereof. This operation is sometimes called a SET operation. Similarly, a change of state from a crystalline state to an amorphous state is achieved by application of an appropriate heating current pulse, wherein the phase change material is heated beyond the melting temperature thereof, and the amorphous state is obtained during the rapid cooling process thereof. This operation is sometimes called a RESET operation. The combination of SET and RESET operations is one means by which data can be written to a phase change memory cell.
Conventionally, resistively switched memories such as phase change memory devices are organized in one or more arrays of phase change cells in a core area of the device, wherein each phase change memory cell is composed of a phase change memory element coupled to a selection switching device. One conventional arrangement is illustrated in FIG. 1, wherein a phase change element 10 is coupled between a bit line 12 and a bipolar select transistor 14. A word line 16 is coupled to the base terminal of the transistor 14. By properly addressing the bit line 12 and word line 16 associated therewith, data may be written thereto and read therefrom. An array of phase change memory cells configured in the manner described above is sometimes called a NOR type memory array.